Espressif Systems /ESP32-C3 /SPI0 /CTRL

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Interpret as CTRL

Description

SPI0 control register.

Fields

FDUMMY_OUT	In the dummy phase the signal level of spi is output by the spi controller.
FCMD_DUAL	Apply 2 signals during command phase 1:enable 0: disable
FCMD_QUAD	Apply 4 signals during command phase 1:enable 0: disable
FASTRD_MODE	This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
FREAD_DUAL	In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
Q_POL	The bit is used to set MISO line polarity, 1: high 0, low
D_POL	The bit is used to set MOSI line polarity, 1: high 0, low
FREAD_QUAD	In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
WP	Write protect signal output when SPI is idle. 1: output high, 0: output low.
FREAD_DIO	In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
FREAD_QIO	In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.

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